Processors

DOMAIN-SPECIFIC MICRO-PROCESSORS

Ranging from low-level application and architecture optimizations to high-level modeling and exploration concerns, M.A utilizes essential research on various levels of abstraction appearing in embedded systems and software design. It promotes platform-based design for improved system implementation and modeling and enhanced performance and cost analyses. Domain-Specific Processors relies upon notions of concurrency and parallelism to satisfy performance and cost constraints resulting from increasingly complex applications and architectures and addresses concepts in specification, simulation, and verification in embedded systems and software design and are used to optimize the efficiency of our various detection systems.

We present a semi-automated method for the detection and exploitation of application domain specific instruction
set extensions for embedded (VLIW) processors. It consists of three steps: the first step detects frequently occurring operation patterns, in the second step, the patterns are grouped and implemented in a number of Special Function Units (SFUs) and the third step incorporates the custom operations into the code
generation process. Experiments show that the SFUs generated and exploited with our methodology can result in architectures that perform up to 30% better than architectures of the same cost without SFUs.
Modern microprocessors require an immense investment of time and effort to create and verify, from the high level
architectural design downwards. We are exploring ways to increase the productivity of design engineers by creating a domain specific language for specifying and simulating processor architectures. We believe that the structuring
principles used in modern functional programming languages, such as static typing, parametric polymorphism, first class functions, and lazy evaluation provide a good formalism for such a domain specific language, and have made initial progress by creating a library on top of the functional language Haskell. We have specified the integer subset of an out of order, superscalar DLX microprocessor, with register renaming, a reorder buffer, a global reservation station, multiple execution units, and speculative branch execution. Two key abstractions of this library are the signal abstract data type (ADT), which models the simulation history of a wire, and the transaction ADT, which models the state of an entire instruction as it travels through the microprocessor.

We see, monitor, evolve and upgrade our processors based on the technology era we are going through, the future, the market and the search for products to make our lives easier. MA LTD can advise you and create according to your needs and your specifications, always with the comprehensive help of our scientists so that everything is done correctly, feasible and with an amazing result.